Exemplary embodiments of the present invention relate to fabricating a conductive layer in a semiconductor device, and more particularly to fabricating a conductive layer having a low contact resistance in a semiconductor device using a chemical vapor deposition (CVD) process.
In a semiconductor device, active elements are disposed over a silicon substrate, and, if necessary, passive elements such as capacitors are also disposed over the silicon substrate together with the active elements. Electric connection paths for signal transfers may be required between two elements where each element may be active or passive. Typically, the electrical connection paths are formed by disposing conductive layers between the elements in a contact structure.
FIG. 1 is a cross-sectional view of landing plug contacts in a semiconductor device. Referring to FIG. 1, device isolation layers 102 define an active region in a silicon substrate 100, and impurity regions 112 and 114 are disposed within the active region. Each area between the impurity regions 112 and 114 defines a channel region where a channel is formed under a predetermined condition. A gate stack 120 is disposed over each channel region. The gate stack 120 includes a gate dielectric layer 121, a gate conductive layer 122, and a gate hard mask layer 123. A gate spacer layer 130 is formed at each sidewall of the gate stack 120. Landing plug contacts 142 and 144 are formed over the impurity regions 112 and 114 which are exposed by the gate stack 120 and the gate spacer layers 130. The landing plug contacts 142 and 144 are conductive layers that are coupled to a storage node contact and a bit line contact in order that the landing plug contacts 142 and 144 are coupled to a capacitor and a bit line, respectively. In FIG. 1, the landing plug contact 142 is coupled to the bit line contact, and the land plug contact 144 is coupled to the storage node contact.
The landing plug contacts 142 and 144 are usually formed using polycrystalline silicon because of its sufficient conductivity. A chemical vapor deposition (CVD) process, and in particular, a low pressure CVD (LPCVD) process is commonly used to form the landing plug contacts 142 and 144.
FIG. 2 is a graph of temperature inside a chamber during a LPCVD process of forming a conductive polycrystalline silicon layer. In FIG. 2, line 210 shows an inside temperature of an LPCVD chamber. A silicon substrate 100 is loaded in to an LPCVD chamber during a loading period t1 when a loading temperature A1 is maintained. The loading temperature A1 may be, for example, approximately 400° C.
The inside temperature of the chamber is increased to a process temperature A2 during a temperature rise period t2. After the inside temperature of the chamber is increased to the process temperature A2, the chamber temperature is maintained at temperature A2 during a temperature stabilization period t3. After the temperature stabilization period t3, a source gas such as, for example, silane (SiH4), is supplied in to the chamber together with an impurity source gas such as, for example, phosphine (PH3). When these source gases are supplied into the chamber, silicon nuclei may form on the silicon substrate, and coalescing may occur around the silicon nuclei to thereby form a polycrystalline silicon layer.
In the above conventional process, the loading temperature A1 of the chamber is set to a temperature of approximately 400° C. However, during the loading period t1, an undesirable natural oxide layer may form on the surface of the silicon substrate to a thickness, for example, of approximately 1 Å. The natural oxide layer may increase the resistance of the landing plug contacts 142 and 144 formed by deposition of the polycrystalline silicon layer.